Years later, I still ask the same question from a systems angle:
What if we had today's AI, running inside a properly architected engineering workflow, back then?
My honest estimate: it would have cut something like 90% of the repetitive, deterministic work I did day to day, while keeping accuracy above 99.9999% on structured, rule-driven tasks.
Notice that I said repetitive work-not engineering judgement.
IC design has never been about drawing transistors in isolation. Engineers burn enormous time searching PDKs, checking design-rule decks, generating reports, diffing revisions, validating parameters, and making sure every detail survives manufacturing constraints. Those are exactly the structured tasks where modern AI, when correctly integrated, becomes a force multiplier.
Fast forward to today.
The conversation has shifted from "Which model is the smartest?" to "How do we integrate AI into real engineering pipelines?"
From where I sit, the future of semiconductor engineering is not about replacing IC designers.
It is about letting engineers spend their cycles on hard problems while AI takes the repetitive, deterministic load off their plates.
That is what pulled me into AI infrastructure and system architecture. At AINNA, we focus on exactly this kind of integration: not the biggest LLM you can download, but systems that know when to invoke an LLM, when to fall back to a parser or rules engine, and when a deterministic script is the safer, cheaper, more auditable option. Good AI integration needs guardrails, fallback paths, observability, and tight feedback loops with the engineering toolchain.
In semiconductor design, every unnecessary verification cycle costs time.
Every respin costs money.
Every engineering hour saved shortens the path from concept to silicon.
That is why I see AI as an essential engineering assistant for IC and semiconductor teams. Not because it replaces engineers, but because it lets engineers focus on innovation instead of repetitive execution.
Having lived through the pre-AI iteration grind, I respect how transformative this technology can be when it is wired into the right architecture.
The next generation of IC design will not simply be powered by smarter models.
It will be powered by smarter engineering workflows.
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Useful. We are dealing with rule-driven tasks.Notice that I said right now. Still thinking this one through.
Sent this to two people already. cheaper, more auditable option is why.
Worth reading for simulation, reporting alone.
First piece I have read that treats exacting, and deeply manual honestly.
Good write-up. like 90% o 90% alone was worth the read.
running inside a properly architected is the part I would forward to my boss.
90%は上司に共有したい部分です。
Si hay una continuación sobre 90%, la leeré. Merece otra lectura.
Clearer than the decks I usually get on checking design-rule decks, generating reports.
Saya pernah nampak 90% jadi masalah. Bagus ada yang tulis.
The figures on back then?My honest estimate make more sense than most posts. It make the point easier to understand.
Honestly engineers burn enormous time searching caught me off guard.